A Design of Sram Structure for Low Power Using Heterojunction Cmos with Single Bit Line

The Present day workstations, low-power processors, computers and super computers are using fast Static Random Access Memory (SRAMs) and will require, in the future, larger density memories with faster access time and minimum power consumption. Acknowledging the intense requirements for power, in current high performance memories of computing devices, the circuit designers have developed a number of power optimizing techniques which target several sources of energy dissipation in an SRAM. The total power dissipated in a typical SRAM architecture is the active and standby power. The access to the memory cell is performed through word line and bit line. The hetero junction concept of SRAM was simulated. The single bit line for a 16 SRAM cell was implemented in an array fashion and the power results are computed and compared with multiple individual SRAM cell structures .The results show that single bit line results in 2.5 times reduction of power. The simulation results are obtained from tanner 14.1 environments.